How do I run Cadence’s Assura DRC from within AWR’s Design Environment ( AWRDE)? If the command errors or times out, the PC is not connected to the Linux. assura drc rule – Assura Rule deck file – ASSURA to PVS conversion – Assura DRC If necessary, read the assura Physical Verification Command Reference!. I use Assura RCX and need to get extraction output in Spectre fornat but generated See the Assura Command Reference & and User Guide.
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Layout versus schematic checking verifies that the layout matches the schematic.
Assura Drc Rule
Model display in netlists is controlled by the Parasitic Capacitor Models pick list in the Netlisting Options tab this is required by spectre. RCX will extract inductance only within these areas. For smaller sub-micron process sizes below 0. For the rest, I suggest you write a script e.
The Designer’s Guide Community Forum – Parasitic extraction with Assura
The symbols can have any name. The assura language is quite self-explaining. Thanks for your advices.
This is known as two-dimensional extraction 2D. Refer to the reference documentation for examples. Reefrence must complete an Assura? In the event there are multiple nets connecting the same named shape, the majority net will be used.
You must specify all layers in the process file to receive accurate results from RCX. The parasitic devices will cause signal delays. The error message in CIW is: You can review your options while in the technology directory as follows: Import Globals excludes global nets nets with a! Two-dimensional simulation You use capgen to simulate two-dimensional process models: This file is automatically referencd when the RCX Run form is opened.
I assume you use Assura in batch mode? You can also browse by product, release, or document type. Sometimes users have seen rsh connectivity problems due to the Windows Feference, so commnad may want to test this having the Firewall turned off. You specify layer names of various substrates or wells you want capacitors decoupled to: Netlist files will contain parasitic elements and designed devices.
After reading Bernd’s answer, I noticed that I completely misunderstood your initial post In the event there are multiple capacitors decoupling to the same well or referencd from a common net, they will be combined. All the settings can be saved in the technology directory as. If you do not have this feature, contact your local AWR Sales representative for assistance. Scaling allows independence between process file and physical design.
To block parasitic capacitance from gate oxide to epitaxy, you use the -p option. Click a course name. Netlisting is controlled by the config view whether the config view is open or not. The layer s you specify must appear in the lvsfile.
If you select Coupled, all capacitors between two nets are calculated and then merged into a single coupling capacitor. For example, net wrt might be split, resulting in the following netlist header: Sidewall capacitance is formed between the edge of a conductor and another conductor above or below it, or an edge coincident to it.
You can include model names for simulation, include them commented out, or exclude them entirely. You typically use -lexclude for high resistivity conductors such as poly.
Three-dimensional simulation You can use capgen to simulate and compile three-dimensional process models for test structures after running simulation of two-dimensional simulation: The field solver is generally best used for greater accuracy on specific nets.
Each end of the capacitor is connected to a neighboring conductor or substrate. These methods control the quantity and quality of data returned by the extractor.
How to implement a DRC rule file in Assura? I am doing layout in cadence virtuoso tool. By default, all global supplies will be extracted. When running on a Linux system, start Mozilla before running cdsdoc. In either case a reference node Ref Node for substrate coupling must be specified. RCX then connects capacitors to the net segments. The Assura RCX interface reduces the chance of errors introduced by manual work.